The invention pertains to DRAM cell constructions and methods of forming DRAM cells.
Technologies referred to as xe2x80x9csmart cutxe2x80x9d and xe2x80x9cwafer-bondingxe2x80x9d have been utilized to bond monocrystalline silicon materials onto semiconductor substrates. Smart cut technology generally refers to a process in which a material is implanted into a silicon substrate to a particular depth and ultimately utilized to crack the substrate, and wafer bonding technology generally refers to a process in which a first semiconductive substrate is bonded to a second semiconductor substrate.
In particular applications of smart cut and wafer-bonding technology, hydrogen ions (which can be, for example, H+, H2+, D+, D2+) are implanted into a first monocrystalline silicon substrate to a desired depth. The first monocrystalline silicon substrate comprises a silicon dioxide surface, and is bonded to a second monocrystalline substrate through the silicon dioxide surface. Subsequently, the bonded first substrate is subjected to a thermal treatment which causes cleavage along the hydrogen ion implant region to split the first substrate at a pre-defined location. The portion of the first substrate remaining bonded to the second substrate can then be utilized as a silicon-on-insulator (SOI) substrate. An exemplary process is described in U.S. Pat. No. 5,953,622. The SOI substrate is subsequently annealed at a temperature of greater than or equal to 900xc2x0 C. to strengthen chemical coupling within the second substrate.
The present invention encompasses new applications for smart cut and wafer-bonding technology, and new semiconductor structures which can be created utilizing such applications.
In one aspect, the invention encompasses a method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. A second semiconductor substrate provided which comprises a monocrystalline material. The second semiconductor substrate is bonded to the first substrate after forming the first DRAM sub-structures. Second DRAM sub-structures are formed on either the first substrate or the second substrate and in electrical connection with the first DRAM sub-structures. Either the first DRAM sub-structures or the second DRAM sub-structures are transistor gate structures, and the other of the first and second DRAM sub-structures are capacitor structures.
In another aspect, the invention encompasses another method of forming a DRAM cell. A first substrate is formed to comprise first DRAM sub-structures separated from one another by an insulative material. The first DRAM sub-structures define an upper surface. A second semiconductor substrate is provided which comprises a monocrystalline material. The second semiconductor substrate is bonded to the first substrate above the first DRAM sub-structures. Second DRAM sub-structures are formed on the second substrate and in electrical connection with the first DRAM sub-structures. Either the first DRAM sub-structures or the second DRAM sub-structures are transistor gate structures, and the other of the first and second DRAM sub-structures are capacitor structures.
In yet another aspect, the invention encompasses a semiconductor structure which comprises a cell plate layer, a dielectric material over the cell plate layer, and a conductive storage node mass over the dielectric material. The conductive storage node mass, dielectric material and cell plate layer together define a capacitor structure, and a first substrate is defined to encompass the capacitor structure. The semiconductor structure further comprises a monocrystalline silicon substrate bonded to the first substrate and over the storage node mass. Additionally, the semiconductor structure comprises a transistor gate on the monocrystalline silicon substrate and operatively connected with the capacitor structure to define a DRAM cell.